1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
//! Implementation of the AESA peripheral on the SAM4L

use core::cell::Cell;
use kernel::common::VolatileCell;
use kernel::common::take_cell::TakeCell;
use kernel::hil;
use kernel::hil::symmetric_encryption::{AES128_BLOCK_SIZE, AES128_KEY_SIZE};
use kernel::returncode::ReturnCode;
use pm;
use scif;

#[allow(dead_code)]
#[derive(Copy, Clone)]
pub enum ConfidentialityMode {
    ECB = 0,
    CBC,
    CFB,
    OFB,
    CTR,
}

/// The registers used to interface with the hardware
#[repr(C)]
struct AesRegisters {
    ctrl: VolatileCell<u32>,       //       0x00
    mode: VolatileCell<u32>,       //       0x04
    databufptr: VolatileCell<u32>, // 0x08
    sr: VolatileCell<u32>,         //         0x0C
    ier: VolatileCell<u32>,        //        0x10
    idr: VolatileCell<u32>,        //        0x14
    imr: VolatileCell<u32>,        //        0x18
    _reserved0: VolatileCell<u32>, // 0x1C
    key0: VolatileCell<u32>,       //       0x20
    key1: VolatileCell<u32>,       //       0x24
    key2: VolatileCell<u32>,       //       0x28
    key3: VolatileCell<u32>,       //       0x2c
    key4: VolatileCell<u32>,       //       0x30
    key5: VolatileCell<u32>,       //       0x34
    key6: VolatileCell<u32>,       //       0x38
    key7: VolatileCell<u32>,       //       0x3c
    initvect0: VolatileCell<u32>,  //  0x40
    initvect1: VolatileCell<u32>,  //  0x44
    initvect2: VolatileCell<u32>,  //  0x48
    initvect3: VolatileCell<u32>,  //  0x4c
    idata: VolatileCell<u32>,      //      0x50
    _reserved1: [u32; 3],          //          0x54 - 0x5c
    odata: VolatileCell<u32>,      //      0x60
    _reserved2: [u32; 3],          //          0x64 - 0x6c
    drngseed: VolatileCell<u32>,   //   0x70
}

// Section 7.1 of datasheet
const AES_BASE: u32 = 0x400B0000;

const IBUFRDY: u32 = 1 << 16;
const ODATARDY: u32 = 1 << 0;

pub struct Aes<'a> {
    registers: *const AesRegisters,

    client: Cell<Option<&'a hil::symmetric_encryption::Client<'a>>>,
    source: TakeCell<'a, [u8]>,
    dest: TakeCell<'a, [u8]>,

    // An index into `source` (or `dest` if that does not exist),
    // marking how much data has been written to the AESA
    write_index: Cell<usize>,

    // An index into `dest`, marking how much data has been read back from the AESA
    read_index: Cell<usize>,

    // The index just after the last byte of `dest` that should receive encrypted output
    stop_index: Cell<usize>,
}

impl<'a> Aes<'a> {
    pub const fn new() -> Aes<'a> {
        Aes {
            registers: AES_BASE as *const AesRegisters,
            client: Cell::new(None),
            source: TakeCell::empty(),
            dest: TakeCell::empty(),
            write_index: Cell::new(0),
            read_index: Cell::new(0),
            stop_index: Cell::new(0),
        }
    }

    fn enable_clock(&self) {
        unsafe {
            pm::enable_clock(pm::Clock::HSB(pm::HSBClock::AESA));
            scif::generic_clock_enable_divided(
                scif::GenericClock::GCLK4,
                scif::ClockSource::CLK_CPU,
                1,
            );
            scif::generic_clock_enable(scif::GenericClock::GCLK4, scif::ClockSource::CLK_CPU);
        }
    }

    fn disable_clock(&self) {
        unsafe {
            scif::generic_clock_disable(scif::GenericClock::GCLK4);
            pm::disable_clock(pm::Clock::HSB(pm::HSBClock::AESA));
        }
    }

    fn enable_interrupts(&self) {
        let regs: &AesRegisters = unsafe { &*self.registers };
        // We want both interrupts.
        regs.ier.set(IBUFRDY | ODATARDY);
    }

    fn disable_interrupts(&self) {
        let regs: &AesRegisters = unsafe { &*self.registers };

        // Disable both interrupts
        regs.idr.set(IBUFRDY | ODATARDY);
    }

    fn disable_input_interrupt(&self) {
        let regs: &AesRegisters = unsafe { &*self.registers };

        // Tell the AESA not to send an interrupt looking for more input
        regs.idr.set(IBUFRDY);
    }

    fn busy(&self) -> bool {
        let regs: &AesRegisters = unsafe { &*self.registers };

        // Are any interrupts set, meaning an encryption operation is in progress?
        regs.imr.get() & (IBUFRDY | ODATARDY) != 0
    }

    fn set_mode(&self, encrypting: bool, mode: ConfidentialityMode) {
        let regs: &AesRegisters = unsafe { &*self.registers };

        let encrypt = if encrypting { 1 } else { 0 };
        let dma = 0;
        let cmeasure = 0xF;
        regs.mode
            .set(encrypt << 0 | dma << 3 | (mode as u32) << 4 | cmeasure << 16);
    }

    fn input_buffer_ready(&self) -> bool {
        let regs: &AesRegisters = unsafe { &*self.registers };
        let status = regs.sr.get();

        status & (1 << 16) != 0
    }

    fn output_data_ready(&self) -> bool {
        let regs: &AesRegisters = unsafe { &*self.registers };
        let status = regs.sr.get();

        status & (1 << 0) != 0
    }

    fn try_set_indices(&self, start_index: usize, stop_index: usize) -> bool {
        stop_index.checked_sub(start_index).map_or(false, |sublen| {
            sublen % AES128_BLOCK_SIZE == 0 && {
                self.source.map_or_else(
                    || {
                        // The destination buffer is also the input
                        if self.dest.map_or(false, |dest| stop_index <= dest.len()) {
                            self.write_index.set(start_index);
                            self.read_index.set(start_index);
                            self.stop_index.set(stop_index);
                            true
                        } else {
                            false
                        }
                    },
                    |source| {
                        if sublen == source.len()
                            && self.dest.map_or(false, |dest| stop_index <= dest.len())
                        {
                            // We will start writing to the AES from the beginning of `source`,
                            // and end at its end
                            self.write_index.set(0);

                            // We will start reading from the AES into `dest` at `start_index`,
                            // and continue until `stop_index`
                            self.read_index.set(start_index);
                            self.stop_index.set(stop_index);
                            true
                        } else {
                            false
                        }
                    },
                )
            }
        })
    }

    // Copy a block from the request buffer to the AESA input register,
    // if there is a block left in the buffer.  Either way, this function
    // returns true if more blocks remain to send.
    fn write_block(&self) -> bool {
        self.source.map_or_else(
            || {
                // The source and destination are the same buffer
                self.dest.map_or_else(
                    || {
                        debug!("Called write_block() with no data");
                        false
                    },
                    |dest| {
                        let index = self.write_index.get();
                        let more = index + AES128_BLOCK_SIZE <= self.stop_index.get();
                        if !more {
                            return false;
                        }
                        let regs: &AesRegisters = unsafe { &*self.registers };
                        for i in 0..4 {
                            let mut v = dest[index + (i * 4) + 0] as usize;
                            v |= (dest[index + (i * 4) + 1] as usize) << 8;
                            v |= (dest[index + (i * 4) + 2] as usize) << 16;
                            v |= (dest[index + (i * 4) + 3] as usize) << 24;
                            regs.idata.set(v as u32);
                        }
                        self.write_index.set(index + AES128_BLOCK_SIZE);

                        let more =
                            self.write_index.get() + AES128_BLOCK_SIZE <= self.stop_index.get();
                        more
                    },
                )
            },
            |source| {
                let index = self.write_index.get();

                let more = index + AES128_BLOCK_SIZE <= source.len();
                if !more {
                    return false;
                }

                let regs: &AesRegisters = unsafe { &*self.registers };
                for i in 0..4 {
                    let mut v = source[index + (i * 4) + 0] as usize;
                    v |= (source[index + (i * 4) + 1] as usize) << 8;
                    v |= (source[index + (i * 4) + 2] as usize) << 16;
                    v |= (source[index + (i * 4) + 3] as usize) << 24;
                    regs.idata.set(v as u32);
                }

                self.write_index.set(index + AES128_BLOCK_SIZE);

                let more = self.write_index.get() + AES128_BLOCK_SIZE <= source.len();
                more
            },
        )
    }

    // Copy a block from the AESA output register back into the request buffer
    // if there is any room left.  Return true if we are still waiting for more
    // blocks after this
    fn read_block(&self) -> bool {
        self.dest.map_or_else(
            || {
                debug!("Called read_block() with no data");
                false
            },
            |dest| {
                let index = self.read_index.get();
                let more = index + AES128_BLOCK_SIZE <= self.stop_index.get();
                if !more {
                    return false;
                }

                let regs: &AesRegisters = unsafe { &*self.registers };
                for i in 0..4 {
                    let v = regs.odata.get();
                    dest[index + (i * 4) + 0] = (v >> 0) as u8;
                    dest[index + (i * 4) + 1] = (v >> 8) as u8;
                    dest[index + (i * 4) + 2] = (v >> 16) as u8;
                    dest[index + (i * 4) + 3] = (v >> 24) as u8;
                }

                self.read_index.set(index + AES128_BLOCK_SIZE);

                let more = self.read_index.get() + AES128_BLOCK_SIZE <= self.stop_index.get();
                more
            },
        )
    }

    /// Handle an interrupt, which will indicate either that the AESA's input
    /// buffer is ready for more data, or that it has completed a block of output
    /// for us to consume
    pub fn handle_interrupt(&self) {
        if !self.busy() {
            // Ignore errant interrupts, in case it's possible for the AES interrupt flag
            // to be set again while we are in this handler.
            return;
        }

        if self.input_buffer_ready() {
            // The AESA says it is ready to receive another block

            if !self.write_block() {
                // We've now written the entirety of the request buffer,
                // so unsubscribe from input interrupts
                self.disable_input_interrupt();
            }
        }

        if self.output_data_ready() {
            // The AESA says it has a completed block to give us

            if !self.read_block() {
                // We've read back all the blocks, so unsubscribe from
                // all interrupts
                self.disable_interrupts();

                // Alert the client of the completion
                if let Some(client) = self.client.get() {
                    client.crypt_done(self.source.take(), self.dest.take().unwrap());
                }
            }
        }
    }
}

impl<'a> hil::symmetric_encryption::AES128<'a> for Aes<'a> {
    fn enable(&self) {
        let regs: &AesRegisters = unsafe { &*self.registers };

        self.enable_clock();
        regs.ctrl.set(0x01);
    }

    fn disable(&self) {
        let regs: &AesRegisters = unsafe { &*self.registers };

        regs.ctrl.set(0x00);
        self.disable_clock();
    }

    fn set_client(&'a self, client: &'a hil::symmetric_encryption::Client<'a>) {
        self.client.set(Some(client));
    }

    fn set_key(&self, key: &[u8]) -> ReturnCode {
        if key.len() != AES128_KEY_SIZE {
            return ReturnCode::EINVAL;
        }

        let regs: &AesRegisters = unsafe { &*self.registers };

        for i in 0..4 {
            let mut k = key[i * 4 + 0] as usize;
            k |= (key[i * 4 + 1] as usize) << 8;
            k |= (key[i * 4 + 2] as usize) << 16;
            k |= (key[i * 4 + 3] as usize) << 24;
            match i {
                0 => regs.key0.set(k as u32),
                1 => regs.key1.set(k as u32),
                2 => regs.key2.set(k as u32),
                3 => regs.key3.set(k as u32),
                _ => {}
            }
        }

        ReturnCode::SUCCESS
    }

    fn set_iv(&self, iv: &[u8]) -> ReturnCode {
        if iv.len() != AES128_BLOCK_SIZE {
            return ReturnCode::EINVAL;
        }

        let regs: &AesRegisters = unsafe { &*self.registers };

        // Set the initial value from the array.
        for i in 0..4 {
            let mut c = iv[i * 4 + 0] as usize;
            c |= (iv[i * 4 + 1] as usize) << 8;
            c |= (iv[i * 4 + 2] as usize) << 16;
            c |= (iv[i * 4 + 3] as usize) << 24;
            match i {
                0 => regs.initvect0.set(c as u32),
                1 => regs.initvect1.set(c as u32),
                2 => regs.initvect2.set(c as u32),
                3 => regs.initvect3.set(c as u32),
                _ => {}
            }
        }

        ReturnCode::SUCCESS
    }

    fn start_message(&self) {
        if self.busy() {
            return;
        }

        let regs: &AesRegisters = unsafe { &*self.registers };

        regs.ctrl.set((1 << 2) | (1 << 0));
    }

    fn crypt(
        &'a self,
        source: Option<&'a mut [u8]>,
        dest: &'a mut [u8],
        start_index: usize,
        stop_index: usize,
    ) -> Option<(ReturnCode, Option<&'a mut [u8]>, &'a mut [u8])> {
        if self.busy() {
            Some((ReturnCode::EBUSY, source, dest))
        } else {
            self.source.put(source);
            self.dest.replace(dest);
            if self.try_set_indices(start_index, stop_index) {
                self.enable_interrupts();
                None
            } else {
                Some((
                    ReturnCode::EINVAL,
                    self.source.take(),
                    self.dest.take().unwrap(),
                ))
            }
        }
    }
}

impl<'a> hil::symmetric_encryption::AES128Ctr for Aes<'a> {
    fn set_mode_aes128ctr(&self, encrypting: bool) {
        self.set_mode(encrypting, ConfidentialityMode::CTR);
    }
}

impl<'a> hil::symmetric_encryption::AES128CBC for Aes<'a> {
    fn set_mode_aes128cbc(&self, encrypting: bool) {
        self.set_mode(encrypting, ConfidentialityMode::CBC);
    }
}

pub static mut AES: Aes<'static> = Aes::new();