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use core::cell::Cell;
use kernel::ReturnCode;
use kernel::common::regs::{ReadOnly, ReadWrite, WriteOnly};
use kernel::hil;
use pm::{self, Clock, PBAClock};
#[repr(C)]
pub struct DacRegisters {
pub cr: WriteOnly<u32, Control::Register>,
pub mr: ReadWrite<u32, Mode::Register>,
pub cdr: WriteOnly<u32, ConversionData::Register>,
pub ier: WriteOnly<u32, InterruptEnable::Register>,
pub idr: WriteOnly<u32, InterruptDisable::Register>,
pub imr: ReadOnly<u32, InterruptMask::Register>,
pub isr: ReadOnly<u32, InterruptStatus::Register>,
_reserved0: [u32; 50],
pub wpmr: ReadWrite<u32, WriteProtectMode::Register>,
pub wpsr: ReadOnly<u32, WriteProtectStatus::Register>,
_reserved1: [u32; 4],
pub version: ReadOnly<u32, Version::Register>,
}
register_bitfields![u32,
Control [
SWRST 0
],
Mode [
CLKDIV OFFSET(16) NUMBITS(16) [],
STARTUP OFFSET( 8) NUMBITS(8) [],
WORD OFFSET( 5) NUMBITS(1) [
HalfWordTransfer = 0b0,
FullWordTransfer = 0b1
],
DACEN OFFSET( 4) NUMBITS(1) [],
TRGSEL OFFSET( 1) NUMBITS(3) [
ExternalTrigger = 0b000,
PeripheralTrigger = 0b001
],
TRGEN OFFSET( 0) NUMBITS(1) [
InternalTrigger = 0b0,
ExternalTrigger = 0b1
]
],
ConversionData [
DATA OFFSET(0) NUMBITS(32) []
],
InterruptEnable [
TXRDY 0
],
InterruptDisable [
TXRDY 0
],
InterruptMask [
TXRDY 0
],
InterruptStatus [
TXRDY 0
],
WriteProtectMode [
WPKEY OFFSET(8) NUMBITS(24) [],
WPEN OFFSET(0) NUMBITS(1) []
],
WriteProtectStatus [
WPROTADDR OFFSET(8) NUMBITS(8) [],
WPROTERR OFFSET(0) NUMBITS(1) []
],
Version [
VARIANT OFFSET(16) NUMBITS(3) [],
VERSION OFFSET( 0) NUMBITS(12) []
]
];
const BASE_ADDRESS: *mut DacRegisters = 0x4003C000 as *mut DacRegisters;
pub struct Dac {
registers: *mut DacRegisters,
enabled: Cell<bool>,
}
pub static mut DAC: Dac = Dac::new(BASE_ADDRESS);
impl Dac {
const fn new(base_address: *mut DacRegisters) -> Dac {
Dac {
registers: base_address,
enabled: Cell::new(false),
}
}
pub fn handle_interrupt(&mut self) {}
}
impl hil::dac::DacChannel for Dac {
fn initialize(&self) -> ReturnCode {
let regs: &DacRegisters = unsafe { &*self.registers };
if !self.enabled.get() {
self.enabled.set(true);
unsafe {
pm::enable_clock(Clock::PBA(PBAClock::DACC));
}
regs.cr.write(Control::SWRST::SET);
let mr = Mode::WORD::HalfWordTransfer + Mode::STARTUP.val(0xff) + Mode::CLKDIV.val(0x60)
+ Mode::TRGEN::InternalTrigger + Mode::DACEN::SET;
regs.mr.write(mr);
}
ReturnCode::SUCCESS
}
fn set_value(&self, value: usize) -> ReturnCode {
let regs: &DacRegisters = unsafe { &*self.registers };
if !self.enabled.get() {
ReturnCode::EOFF
} else {
if !regs.isr.is_set(InterruptStatus::TXRDY) {
return ReturnCode::EBUSY;
}
regs.cdr.write(ConversionData::DATA.val(value as u32));
ReturnCode::SUCCESS
}
}
}