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use core::cell::Cell;
use core::cmp;
use dma;
use kernel::ReturnCode;
use kernel::common::VolatileCell;
use kernel::hil;
use pm;
#[repr(C)]
struct USARTRegisters {
cr: VolatileCell<u32>,
mr: VolatileCell<u32>,
ier: VolatileCell<u32>,
idr: VolatileCell<u32>,
imr: VolatileCell<u32>,
csr: VolatileCell<u32>,
rhr: VolatileCell<u32>,
thr: VolatileCell<u32>,
brgr: VolatileCell<u32>,
rtor: VolatileCell<u32>,
ttgr: VolatileCell<u32>,
_reserved0: [VolatileCell<u32>; 5],
fidi: VolatileCell<u32>,
ner: VolatileCell<u32>,
_reserved1: VolatileCell<u32>,
ifr: VolatileCell<u32>,
man: VolatileCell<u32>,
linmr: VolatileCell<u32>,
linir: VolatileCell<u32>,
linbrr: VolatileCell<u32>,
_reserved2: [VolatileCell<u32>; 33],
wpmr: VolatileCell<u32>,
wpsr: VolatileCell<u32>,
_reserved3: [VolatileCell<u32>; 4],
version: VolatileCell<u32>,
}
const USART_BASE_ADDRS: [*mut USARTRegisters; 4] = [
0x40024000 as *mut USARTRegisters,
0x40028000 as *mut USARTRegisters,
0x4002C000 as *mut USARTRegisters,
0x40030000 as *mut USARTRegisters,
];
#[derive(Copy, Clone, PartialEq)]
#[allow(non_camel_case_types)]
pub enum USARTStateRX {
Idle,
DMA_Receiving,
}
#[derive(Copy, Clone, PartialEq)]
#[allow(non_camel_case_types)]
pub enum USARTStateTX {
Idle,
DMA_Transmitting,
Transfer_Completing,
}
#[derive(Copy, Clone)]
enum UsartMode {
Uart,
Spi,
Unused,
}
#[derive(Copy, Clone)]
enum UsartClient<'a> {
Uart(&'a hil::uart::Client),
SpiMaster(&'a hil::spi::SpiMasterClient),
}
pub struct USART {
registers: *mut USARTRegisters,
clock: pm::Clock,
usart_mode: Cell<UsartMode>,
usart_tx_state: Cell<USARTStateTX>,
usart_rx_state: Cell<USARTStateRX>,
rx_dma: Cell<Option<&'static dma::DMAChannel>>,
rx_dma_peripheral: dma::DMAPeripheral,
rx_len: Cell<usize>,
tx_dma: Cell<Option<&'static dma::DMAChannel>>,
tx_dma_peripheral: dma::DMAPeripheral,
tx_len: Cell<usize>,
client: Cell<Option<UsartClient<'static>>>,
spi_chip_select: Cell<Option<&'static hil::gpio::Pin>>,
}
pub static mut USART0: USART = USART::new(
USART_BASE_ADDRS[0],
pm::PBAClock::USART0,
dma::DMAPeripheral::USART0_RX,
dma::DMAPeripheral::USART0_TX,
);
pub static mut USART1: USART = USART::new(
USART_BASE_ADDRS[1],
pm::PBAClock::USART1,
dma::DMAPeripheral::USART1_RX,
dma::DMAPeripheral::USART1_TX,
);
pub static mut USART2: USART = USART::new(
USART_BASE_ADDRS[2],
pm::PBAClock::USART2,
dma::DMAPeripheral::USART2_RX,
dma::DMAPeripheral::USART2_TX,
);
pub static mut USART3: USART = USART::new(
USART_BASE_ADDRS[3],
pm::PBAClock::USART3,
dma::DMAPeripheral::USART3_RX,
dma::DMAPeripheral::USART3_TX,
);
impl USART {
const fn new(
base_addr: *mut USARTRegisters,
clock: pm::PBAClock,
rx_dma_peripheral: dma::DMAPeripheral,
tx_dma_peripheral: dma::DMAPeripheral,
) -> USART {
USART {
registers: base_addr,
clock: pm::Clock::PBA(clock),
usart_mode: Cell::new(UsartMode::Unused),
usart_rx_state: Cell::new(USARTStateRX::Idle),
usart_tx_state: Cell::new(USARTStateTX::Idle),
rx_dma: Cell::new(None),
rx_dma_peripheral: rx_dma_peripheral,
rx_len: Cell::new(0),
tx_dma: Cell::new(None),
tx_dma_peripheral: tx_dma_peripheral,
tx_len: Cell::new(0),
client: Cell::new(None),
spi_chip_select: Cell::new(None),
}
}
pub fn set_dma(&self, rx_dma: &'static dma::DMAChannel, tx_dma: &'static dma::DMAChannel) {
self.rx_dma.set(Some(rx_dma));
self.tx_dma.set(Some(tx_dma));
}
pub fn enable_rx(&self) {
self.enable_clock();
let regs: &USARTRegisters = unsafe { &*self.registers };
let cr_val = 0x00000000 | (1 << 4);
regs.cr.set(cr_val);
}
pub fn enable_tx(&self) {
self.enable_clock();
let regs: &USARTRegisters = unsafe { &*self.registers };
let cr_val = 0x00000000 | (1 << 6);
regs.cr.set(cr_val);
}
pub fn disable_rx(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
let cr_val = 0x00000000 | (1 << 5);
regs.cr.set(cr_val);
self.usart_rx_state.set(USARTStateRX::Idle);
if self.usart_tx_state.get() == USARTStateTX::Idle {
self.disable_clock();
}
}
pub fn disable_tx(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
let cr_val = 0x00000000 | (1 << 7);
regs.cr.set(cr_val);
self.usart_tx_state.set(USARTStateTX::Idle);
if self.usart_rx_state.get() == USARTStateRX::Idle {
self.disable_clock();
}
}
pub fn abort_rx(&self, error: hil::uart::Error) {
if self.usart_rx_state.get() == USARTStateRX::DMA_Receiving {
self.disable_rx_interrupts();
self.disable_rx();
self.usart_rx_state.set(USARTStateRX::Idle);
let mut length = 0;
let buffer = self.rx_dma.get().map_or(None, |rx_dma| {
length = self.rx_len.get() - rx_dma.transfer_counter();
let buf = rx_dma.abort_xfer();
rx_dma.disable();
buf
});
self.rx_len.set(0);
self.client.get().map(|usartclient| {
buffer.map(|buf| match usartclient {
UsartClient::Uart(client) => {
client.receive_complete(buf, length, error);
}
UsartClient::SpiMaster(_) => {}
});
});
}
}
pub fn abort_tx(&self, error: hil::uart::Error) {
if self.usart_tx_state.get() == USARTStateTX::DMA_Transmitting {
self.disable_tx_interrupts();
self.disable_tx();
self.usart_tx_state.set(USARTStateTX::Idle);
let mut length = 0;
let buffer = self.tx_dma.get().map_or(None, |tx_dma| {
length = self.tx_len.get() - tx_dma.transfer_counter();
let buf = tx_dma.abort_xfer();
tx_dma.disable();
buf
});
self.tx_len.set(0);
self.client.get().map(|usartclient| {
buffer.map(|buf| match usartclient {
UsartClient::Uart(client) => {
client.receive_complete(buf, length, error);
}
UsartClient::SpiMaster(_) => {}
});
});
}
}
pub fn enable_tx_empty_interrupt(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
regs.ier.set(1 << 9);
}
pub fn disable_tx_empty_interrupt(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
regs.idr.set(1 << 9);
}
pub fn enable_rx_error_interrupts(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
let ier_val = 0x00000000 |
(1 << 7) |
(1 << 6) |
(1 << 5);
regs.ier.set(ier_val);
}
pub fn disable_rx_interrupts(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
let idr_val = 0x00000000 |
(1 << 12) |
(1 << 8) |
(1 << 7) |
(1 << 6) |
(1 << 5) |
(1 << 0);
regs.idr.set(idr_val);
}
pub fn disable_tx_interrupts(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
let idr_val = 0x00000000 |
(1 << 9) |
(1 << 1);
regs.idr.set(idr_val);
}
pub fn disable_interrupts(&self) {
self.disable_rx_interrupts();
self.disable_tx_interrupts();
}
pub fn reset(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
let cr_val = 0x00000000 |
(1 << 8) |
(1 << 3) |
(1 <<2);
regs.cr.set(cr_val);
self.abort_rx(hil::uart::Error::ResetError);
self.enable_clock();
self.abort_tx(hil::uart::Error::ResetError);
}
pub fn handle_interrupt(&self) {
if self.is_clock_enabled() {
let regs: &USARTRegisters = unsafe { &*self.registers };
let status = regs.csr.get();
let mask = regs.imr.get();
regs.cr.set(1 << 8);
if status & (1 << 8) != 0 && mask & (1 << 8) != 0 {
self.disable_rx_timeout();
self.abort_rx(hil::uart::Error::CommandComplete);
} else if status & (1 << 9) != 0 && mask & (1 << 9) != 0 {
self.disable_tx_empty_interrupt();
self.disable_tx();
self.usart_tx_state.set(USARTStateTX::Idle);
} else if status & (1 << 7) != 0 {
self.abort_rx(hil::uart::Error::ParityError);
} else if status & (1 << 6) != 0 {
self.abort_rx(hil::uart::Error::FramingError);
} else if status & (1 << 5) != 0 {
self.abort_rx(hil::uart::Error::OverrunError);
}
}
}
fn enable_clock(&self) {
unsafe {
pm::enable_clock(self.clock);
}
}
fn disable_clock(&self) {
unsafe {
pm::disable_clock(self.clock);
}
}
fn is_clock_enabled(&self) -> bool {
unsafe { pm::is_clock_enabled(self.clock) }
}
fn set_mode(&self, mode: u32) {
let regs: &USARTRegisters = unsafe { &*self.registers };
regs.mr.set(mode);
}
fn set_baud_rate(&self, baud_rate: u32) {
let regs: &USARTRegisters = unsafe { &*self.registers };
let system_frequency = pm::get_system_frequency();
let cd = match self.usart_mode.get() {
UsartMode::Uart => system_frequency / (8 * baud_rate),
UsartMode::Spi => system_frequency / baud_rate,
_ => 0,
};
regs.brgr.set(cd);
}
fn rts_enable_spi_assert_cs(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
regs.cr.set(1 << 18);
}
fn rts_disable_spi_deassert_cs(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
regs.cr.set(1 << 19);
}
fn enable_rx_timeout(&self, timeout: u8) {
let regs: &USARTRegisters = unsafe { &*self.registers };
let rtor_val: u32 = 0x00000000 | timeout as u32;
regs.rtor.set(rtor_val);
regs.ier.set((1 << 8));
regs.cr.set((1 << 11));
}
fn disable_rx_timeout(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
regs.rtor.set(0);
regs.idr.set((1 << 8));
}
fn enable_rx_terminator(&self, _terminator: u8) {
panic!("didn't write terminator stuff yet");
}
pub fn send_byte(&self, byte: u8) {
let regs: &USARTRegisters = unsafe { &*self.registers };
let thr_val: u32 = 0x00000000 | byte as u32;
regs.thr.set(thr_val);
}
pub fn tx_ready(&self) -> bool {
let regs: &USARTRegisters = unsafe { &*self.registers };
let csr_val: u32 = regs.csr.get();
let mut ret_val = false;
if (csr_val & (1 << 1)) == (1 << 1) {
ret_val = true;
}
ret_val
}
}
impl dma::DMAClient for USART {
fn xfer_done(&self, pid: dma::DMAPeripheral) {
match self.usart_mode.get() {
UsartMode::Uart => {
if pid == self.rx_dma_peripheral {
self.disable_rx_interrupts();
self.disable_rx();
self.usart_rx_state.set(USARTStateRX::Idle);
let buffer = self.rx_dma.get().map_or(None, |rx_dma| {
let buf = rx_dma.abort_xfer();
rx_dma.disable();
buf
});
self.client.get().map(|usartclient| {
buffer.map(|buf| {
let length = self.rx_len.get();
match usartclient {
UsartClient::Uart(client) => {
client.receive_complete(
buf,
length,
hil::uart::Error::CommandComplete,
);
}
UsartClient::SpiMaster(_) => {}
}
});
});
self.rx_len.set(0);
} else if pid == self.tx_dma_peripheral {
self.usart_tx_state.set(USARTStateTX::Transfer_Completing);
self.enable_tx_empty_interrupt();
let buffer = self.tx_dma.get().map_or(None, |tx_dma| {
let buf = tx_dma.abort_xfer();
tx_dma.disable();
buf
});
self.client.get().map(|usartclient| {
buffer.map(|buf| match usartclient {
UsartClient::Uart(client) => {
client.transmit_complete(buf, hil::uart::Error::CommandComplete);
}
UsartClient::SpiMaster(_) => {}
});
});
self.tx_len.set(0);
}
}
UsartMode::Spi => {
if (self.usart_rx_state.get() == USARTStateRX::Idle
&& pid == self.tx_dma_peripheral)
|| pid == self.rx_dma_peripheral
{
self.spi_chip_select.get().map_or_else(
|| {
self.rts_disable_spi_deassert_cs();
},
|cs| {
cs.set();
},
);
self.usart_tx_state.set(USARTStateTX::Transfer_Completing);
self.enable_tx_empty_interrupt();
self.usart_rx_state.set(USARTStateRX::Idle);
self.disable_rx();
let txbuf = self.tx_dma.get().map_or(None, |dma| {
let buf = dma.abort_xfer();
dma.disable();
buf
});
let rxbuf = self.rx_dma.get().map_or(None, |dma| {
let buf = dma.abort_xfer();
dma.disable();
buf
});
let len = self.tx_len.get();
self.client.get().map(|usartclient| {
txbuf.map(|tbuf| match usartclient {
UsartClient::Uart(_) => {}
UsartClient::SpiMaster(client) => {
client.read_write_done(tbuf, rxbuf, len);
}
});
});
self.tx_len.set(0);
}
}
_ => {}
}
}
}
impl hil::uart::UART for USART {
fn set_client(&self, client: &'static hil::uart::Client) {
let c = UsartClient::Uart(client);
self.client.set(Some(c));
}
fn init(&self, params: hil::uart::UARTParams) {
self.usart_mode.set(UsartMode::Uart);
self.enable_clock();
self.disable_interrupts();
self.reset();
self.enable_clock();
let mut mode = 0x00000000;
mode |= 0x1 << 19;
mode |= 0x3 << 6;
mode |= 0x0 << 4;
match params.stop_bits {
hil::uart::StopBits::One => mode |= 0x0 << 12,
hil::uart::StopBits::Two => mode |= 0x2 << 12,
};
match params.parity {
hil::uart::Parity::None => mode |= 0x4 << 9,
hil::uart::Parity::Odd => mode |= 0x1 << 9,
hil::uart::Parity::Even => mode |= 0x0 << 9,
};
if params.hw_flow_control {
mode |= 0x2 << 0;
} else {
mode |= 0x0 << 0;
}
self.set_mode(mode);
self.set_baud_rate(params.baud_rate);
self.disable_clock();
}
fn transmit(&self, tx_data: &'static mut [u8], tx_len: usize) {
self.enable_clock();
self.abort_tx(hil::uart::Error::RepeatCallError);
self.enable_tx();
self.usart_tx_state.set(USARTStateTX::DMA_Transmitting);
self.tx_dma.get().map(move |dma| {
dma.enable();
dma.do_xfer(self.tx_dma_peripheral, tx_data, tx_len);
self.tx_len.set(tx_len);
});
}
fn receive(&self, rx_buffer: &'static mut [u8], rx_len: usize) {
self.enable_clock();
self.abort_rx(hil::uart::Error::RepeatCallError);
let mut length = rx_len;
if rx_len > rx_buffer.len() {
length = rx_buffer.len();
}
self.enable_rx();
self.enable_rx_error_interrupts();
self.usart_rx_state.set(USARTStateRX::DMA_Receiving);
self.rx_dma.get().map(move |dma| {
dma.enable();
dma.do_xfer(self.rx_dma_peripheral, rx_buffer, length);
self.rx_len.set(rx_len);
});
}
}
impl hil::uart::UARTAdvanced for USART {
fn receive_automatic(&self, rx_buffer: &'static mut [u8], interbyte_timeout: u8) {
self.enable_clock();
self.abort_rx(hil::uart::Error::RepeatCallError);
self.enable_rx();
self.enable_rx_error_interrupts();
self.usart_rx_state.set(USARTStateRX::DMA_Receiving);
self.enable_rx_timeout(interbyte_timeout);
self.rx_dma.get().map(move |dma| {
dma.enable();
let length = rx_buffer.len();
dma.do_xfer(self.rx_dma_peripheral, rx_buffer, length);
self.rx_len.set(length);
});
}
fn receive_until_terminator(&self, rx_buffer: &'static mut [u8], terminator: u8) {
self.enable_clock();
self.abort_rx(hil::uart::Error::RepeatCallError);
self.enable_rx();
self.enable_rx_error_interrupts();
self.usart_rx_state.set(USARTStateRX::DMA_Receiving);
self.enable_rx_terminator(terminator);
self.rx_dma.get().map(move |dma| {
dma.enable();
let length = rx_buffer.len();
dma.do_xfer(self.rx_dma_peripheral, rx_buffer, length);
self.rx_len.set(length);
});
}
}
impl hil::spi::SpiMaster for USART {
type ChipSelect = Option<&'static hil::gpio::Pin>;
fn init(&self) {
let regs: &USARTRegisters = unsafe { &*self.registers };
self.usart_mode.set(UsartMode::Spi);
self.enable_clock();
self.set_baud_rate(2000000);
let mode =
0xe << 0
| 0 << 4
| 0x3 << 6
| 0x4 << 9
| 1 << 18 ;
self.set_mode(mode);
regs.ttgr.set(4);
self.disable_clock();
}
fn set_client(&self, client: &'static hil::spi::SpiMasterClient) {
let c = UsartClient::SpiMaster(client);
self.client.set(Some(c));
}
fn is_busy(&self) -> bool {
return false;
}
fn read_write_bytes(
&self,
mut write_buffer: &'static mut [u8],
read_buffer: Option<&'static mut [u8]>,
len: usize,
) -> ReturnCode {
self.enable_tx();
self.enable_rx();
let buflen = read_buffer.as_ref().map_or(write_buffer.len(), |rbuf| {
cmp::min(rbuf.len(), write_buffer.len())
});
let count = cmp::min(buflen, len);
self.tx_len.set(count);
self.spi_chip_select.get().map_or_else(
|| {
self.rts_enable_spi_assert_cs();
},
|cs| {
cs.clear();
},
);
if read_buffer.is_some() {
read_buffer.map(|rbuf| {
self.tx_dma.get().map(move |dma| {
self.rx_dma.get().map(move |read| {
self.usart_tx_state.set(USARTStateTX::DMA_Transmitting);
self.usart_rx_state.set(USARTStateRX::Idle);
dma.enable();
dma.do_xfer(self.tx_dma_peripheral, write_buffer, count);
self.usart_rx_state.set(USARTStateRX::DMA_Receiving);
read.enable();
read.do_xfer(self.rx_dma_peripheral, rbuf, count);
});
});
});
} else {
self.tx_dma.get().map(move |dma| {
self.usart_tx_state.set(USARTStateTX::DMA_Transmitting);
self.usart_rx_state.set(USARTStateRX::Idle);
dma.enable();
dma.do_xfer(self.tx_dma_peripheral, write_buffer, count);
});
}
ReturnCode::SUCCESS
}
fn write_byte(&self, val: u8) {
let regs: &USARTRegisters = unsafe { &*self.registers };
self.enable_clock();
regs.cr.set((1 << 4) | (1 << 6));
regs.thr.set(val as u32);
}
fn read_byte(&self) -> u8 {
let regs: &USARTRegisters = unsafe { &*self.registers };
self.enable_clock();
regs.rhr.get() as u8
}
fn read_write_byte(&self, val: u8) -> u8 {
let regs: &USARTRegisters = unsafe { &*self.registers };
self.enable_clock();
regs.cr.set((1 << 4) | (1 << 6));
regs.thr.set(val as u32);
while regs.csr.get() & (1 << 0) == 0 {}
regs.rhr.get() as u8
}
fn specify_chip_select(&self, cs: Self::ChipSelect) {
self.spi_chip_select.set(cs);
}
fn set_rate(&self, rate: u32) -> u32 {
self.enable_clock();
self.set_baud_rate(rate);
let system_frequency = pm::get_system_frequency();
let cd = system_frequency / rate;
system_frequency / cd
}
fn get_rate(&self) -> u32 {
let regs: &USARTRegisters = unsafe { &*self.registers };
self.enable_clock();
let system_frequency = pm::get_system_frequency();
let cd = regs.brgr.get() & 0xFFFF;
system_frequency / cd
}
fn set_clock(&self, polarity: hil::spi::ClockPolarity) {
let regs: &USARTRegisters = unsafe { &*self.registers };
self.enable_clock();
let mode = regs.mr.get();
match polarity {
hil::spi::ClockPolarity::IdleLow => {
regs.mr.set(mode & !(1 << 16));
}
hil::spi::ClockPolarity::IdleHigh => {
regs.mr.set(mode | (1 << 16));
}
}
}
fn get_clock(&self) -> hil::spi::ClockPolarity {
let regs: &USARTRegisters = unsafe { &*self.registers };
self.enable_clock();
let mode = regs.mr.get();
match mode & (1 << 16) {
0 => hil::spi::ClockPolarity::IdleLow,
_ => hil::spi::ClockPolarity::IdleHigh,
}
}
fn set_phase(&self, phase: hil::spi::ClockPhase) {
let regs: &USARTRegisters = unsafe { &*self.registers };
self.enable_clock();
let mode = regs.mr.get();
match phase {
hil::spi::ClockPhase::SampleLeading => {
regs.mr.set(mode | (1 << 8));
}
hil::spi::ClockPhase::SampleTrailing => {
regs.mr.set(mode & !(1 << 8));
}
}
}
fn get_phase(&self) -> hil::spi::ClockPhase {
let regs: &USARTRegisters = unsafe { &*self.registers };
self.enable_clock();
let mode = regs.mr.get();
match mode & (1 << 8) {
0 => hil::spi::ClockPhase::SampleLeading,
_ => hil::spi::ClockPhase::SampleTrailing,
}
}
fn hold_low(&self) {
unimplemented!("USART: SPI: Use `read_write_bytes()` instead.");
}
fn release_low(&self) {
unimplemented!("USART: SPI: Use `read_write_bytes()` instead.");
}
}